H3 coprocessor response problem

ImmortanJoe

A little background. I'm trying to port RISC OS Open to Orange Pi PC, and later other variants I hope. I've been wasting huge amounts of time trying to track down instability and undefined instruction aborts. Every time the problem seems to originate from coprocessor instructions. It seems to be a random issue, like sometimes a coprocessor isn't ready to accept an instruction so it falls through to an undefined instruction abort. It's maddening!
Does anybody know if the coprocessors (Mostly seems to be MMU and cache related) need some kind of special handling that I'm not aware of?

igorpec

Better to ask here: http://linux-sunxi.org/Mailing_list

ImmortanJoe

I considered that, but it's badly off topic. RISC OS has absolutely nothing in common with Linux. Not sure how that would go on a mailing list.

rpidmx512

I have the following code examples, which are working perfectly. I have no issues with CP15. I am about to implement the page table. I will let you know the outcomd.

1. reset:
   
2.     @set VBAR
   
3.     ldr   r0, =_start
   
4.     mcr   p15, 0, r0, c12, c0, 0
   

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1.         @ Bit 2 is set by U-Boot
   
2.     mrc p15, 0, r0, c1, c0, 0
   
3.         bic r0,r0, #0x0002                         @ Allow misalignment (Bit 2)
   
4.     mcr p15, 0, r0, c1, c0, 0
   

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1. const bool arm_install_handler(unsigned routine, unsigned *vector) {
   
2.         unsigned vector_table;
   
3.         asm volatile ("mrc p15, 0, %0, c12, c0, 0" : "=r" (vector_table));
   
4. 
   
5.         const unsigned vec = (((routine - vector_table) - (unsigned) vector - 0x8) >> 2);
   
6. 
   
7.         if (vec & 0xff000000) {
   
8.                 return false;
   
9.         }
   
10. 
    
11.         const unsigned v = (unsigned) vector + vector_table;
    
12.         *(unsigned *) v = (0xea000000 | vec);
    
13. 
    
14.         invalidate_instruction_cache();
    
15.         isb();
    
16. 
    
17.         return true;
    
18. }
    

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